A flip-flop is a component commonly used in microelectronics to store a binary value or “state”. A common way of producing it is to assemble two latches, respectively called a master latch and a slave latch. A latch is typically a bistable circuit, of which the structure, known in itself, includes two inverters connected head-to-tail. One or the other or both of these inverters can be tristate inverters.
The flip-flop has two distinct periods:                a transparent period during a short time window around an edge of the clock signal, during which an input data item can be transferred to the level of the flip-flop output, and        a storage period, in which the latch maintains the state of its output regardless of the input data. During this period, the output of the latch therefore provides the most recent information that has passed through it in its previous transparent state.        
In the case of a flip-flop triggered on a rising clock edge, the first latch (master) is transparent when the clock signal is at low level (logic 0) and in storage mode when the clock signal is at high level (logic 1). The second latch (slave) is transparent when the clock signal is high level and in storage mode when the clock signal is at low level. Thus, the resulting latch is transparent during the rising edge of the clock signal.
An example of this type of latch, based on a so-called “Hybrid Latch Flip-Flop” (HLFF) architecture, is presented in the article “Flow-through latch and edge triggered flip-flop hybrid elements” of H. Partovi et al., IEEE 1996, International Solid State Circuit Conference, which is incorporated by reference.
FIG. 1 shows an embodiment according to the prior art of the master latch of an HLFF-type flip-flop. The operation of this latch is based on the use of a delayed clock signal. To this end, the bistable structure of the master latch integrates a delay chain based on CH inverters. The delay chain CH includes three series-connected inverters I1, I2 and I3. The inverter I1 receives, at the input, the clock signal CLK, so that the inverse clock signal CLK/ delayed three times through the three inverters I1, I2 and I3 is generated at the output of the inverter chain.
In the detail, a first inverter of the bistable circuit of FIG. 1 is constituted by a pMos-type transistor P1, of which a source is connected to a power supply source Vdd of the circuit and of which a gate is connected to the clock input CLK of the circuit, and three nMos-type transistors, respectively MN1, MN2 and MN3, connected in series between the drain of the transistor P1 and a ground of the circuit. The gate of transistor MN1 is controlled by the delayed inverse clock signal CLK/ delivered at the output of the delay chain CH. The gate of transistor MN2 is controlled by an input data item Data and the gate of transistor MN3 is controlled by the clock signal CLK. The common point M of transistors P1 and MN1 is connected to the input of a second inverter of the bistable circuit providing the output Out and by means of which the first inverter is looped back to its input.
The second inverter is formed by three Mos transistors P2, N2 and N3, connected in series between the supply voltage Vdd and a ground of the circuit. In the detail, the pMos-type transistor P2 has its source connected to the power supply voltage Vdd of the circuit, and its drain connected to the drain of the nMos-type transistor N2 so as to provide the output Out, with the gates of transistors P2 and N2 being connected together to the intermediate node M of the bistable circuit. The source of transistor N2 is connected to the drain of the nMos-type transistor N3, of which the source is connected to the ground of the circuit and of which the gate is connected to the clock input CLK of the circuit.
The operation of the circuit of FIG. 1 is as follows. When the clock signal CLK is at low level, the node M is pre-charged to Vdd by means of transistor P1 which is turned on, with the path to the ground being closed by means of transistor MN3, which is off, whereas transistor MN1 is on due to the inverse clock signal CLK/ at high level applied to its gate.
In a next clock edge, the signal CLK switches to high level. Transistor MN3 is then turned on. As the inverter-based delay chain CH creates a certain delay, the inverse clock signal CLK/ applied to the gate of MN1 is therefore kept at high level for the duration of this delay, leaving transistor MN1 on. During the delay created by the delay chain CH, there is therefore a time window during which transistors MN1 and MN3 are simultaneously on. At the end of this delay, the delayed clock signal CLK/ will drop to low level, then controlling the closing of the path constituted by the nMos transistors MN1, MN2 and MN3.
Thus, during the short time window available around the clock edge following the pre-charge phase during which transistors MN1 and MN3 are simultaneously on:                if the data input signal Data is at low level, the path of the nMos transistors MN1 to MN3 is blocked and the intermediate node M is kept at high level at its pre-charge value. A logic 0 is then transmitted to the level of the output Out, since the two nMos N2 and N3 are on;        if, on the other hand, the data input signal Data is at high level, MN2 is turned on, which opens the path of transistors MN1 to MN3 and the intermediate node M is discharged (pulled to the ground) by means of the three transistors MN1 to MN3. A logic 1 is then transmitted to the level of the output Out, and transistor N2 is again turned off while P2 is on.        
The flip-flop is therefore transparent for the duration of the delay created by the delay chain, defining a time window in which both the clock and the delayed clock are at the high level, enabling the input data to be transferred to the output.
This structure is advantageous owing to the switching speed due to the pre-charge of the node M, but it is limited by the difficulty of obtaining the time window, defining a period of latch transparency that is long enough to allow the discharge of the node M.
Indeed, it is possible to have a situation in which the transistors MN1, MN2 and MN3 forming the discharge means of the node M are rather slow, while the inverters I1, I2 and I3 are rather fast. A configuration of this type can lead to an unfavorable situation, in which the time needed to discharge the node M through the battery MN1/MN2/MN3 is greater than the duration of the time window provided by the chain of inverters I1, I2, I3 during which transistor MN1 of the discharge battery is kept on. More specifically, as the inverter chain is rather fast, during a rising clock edge, it does not make it possible to produce a sufficiently long delay, which means that the delayed clock signal falls too quickly to be able to give the battery of nMos MN1, MN2 and MN3 the time to discharge the node M when the data signal Data is at the high level.
This defective operation of the latch can be explained by mismatches of the Mos transistors used, on the one hand, in the inverter-based delay chain CH and, on the other hand, in the path of nMos MN1, MN2 and MN3, occurring in their production. Thus, problems of repeatability in the transistor production method can mean that Mos transistors have characteristics that diverge with respect to those expected, which distorts the performance expected in terms of the current capable of being drawn by the Mos respectively from the inverter chain CH and the path MN1/MN2/MN3, capable of resulting in a defective operation in terms of the assembly's dynamics, as explained above.
One way of overcoming these undesirable effects related to mismatches is to have the delay produced by the delay chain be longer than the discharge time of the longest node M engaged by the transistor path MN1/MN2/MN3. One way of delaying the inverter chain CH in order to prepare for this worst-case scenario is to adjust the W/L ratio (W being the width and L being the length) of the transistors of the inverter chain CH so as to reduce the amount of current passed through by each of them.
However, such a choice intended to take into account in the delay chain worst-case delay of the discharge path MN1/MN2/MN3, while ensuring that the node M has the time necessary to be discharged through the path MN1/MN2/MN3, may impair the performance of the latch. Indeed, by thus increasing the duration of the time window defined by the delay chain, the duration of the transparency window of the latch, and therefore also the time of establishing and of maintaining the input data are increased, which may adversely affect the use of the latch, since it means that the input data must be held for a longer time, according to the time during which the inverter chain CH has not yet turned off the transistor MN1.
This choice of adjusting the W/L ratio of the transistors of the inverter chain with respect to the W/L ratio of the transistors of the path MN1/MN2/MN3, also has the disadvantage of not being capable of being implemented in all transistor production processes.